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smp04Cspecifications electrical characteristics parameter symbol conditions min typ max units linearity error 0.01 % buffer offset voltage v os v in = 6 v C10 2.5 +10 mv hold step v hs v in = 6 v, t a = +25 c to +85 c2.54mv v in = 6 v, t a = C40 c5mv droop rate d v/ d tv in = 6 v, t a = +25 c 2 25 mv/s output source current 1 i source v in = 6 v 1.2 ma output sink current 1 i sink v in = 6 v 0.5 ma output voltage range ovr r l = 20 k w 0.06 10.0 v r l = 10 k w 0.06 9.5 v logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in 0.5 1 m a dynamic performance 2 acquisition time 3 t aq t a = +25 c, 0 v to 10 v step to 0.1% 3.5 4.25 m s C40 c t a +85 c 3.75 5.25 m s acquisition time 3 t aq t a = +25 c, 0 v to 10 v step to 0.01% 9 m s hold mode settling time t h to 1 mv 1 m s slew rate 4 sr r l = 20 k w 34 v/ m s capacitive load stability c l <30% overshoot 500 pf analog crosstalk 0 v to 10 v step C80 db supply characteristics power supply rejection ratio psrr 10.8 v v dd 13.2 v 60 75 db supply current i dd 47 ma power dissipation p dis 84 mw electrical characteristics parameter symbol conditions min typ max units linearity error 0.01 % buffer offset voltage v os v in = 0 v C10 2.5 +10 mv hold step v hs v in = 0 v, t a = +25 c to +85 c2.54mv v in = 0 v, t a = C40 c5mv droop rate d v/ d tv in = 0 v, t a = +25 c 2 25 mv/s output resistance r out 1 w output source current 1 i source v in = 0 v 1.2 ma output sink current 1 i sink v in = 0 v 0.5 ma output voltage range ovr r l = 20 k w C3.0 +3.0 v logic characteristics logic input high voltage v inh 2.4 v logic input low voltage v inl 0.8 v logic input current i in 0.5 1 m a dynamic performance 2 acquisition time 3 t aq C3 v to +3 v step to 0.1% 3.6 11 m s acquisition time 3 t aq C3 v to +3 v step to 0.01% 9 m s hold mode settling time t h to 1 mv 1 m s slew rate 5 sr r l = 20 k w 3v/ m s capacitive load stability c l <30% overshoot 500 pf supply characteristics power supply rejection ratio psrr 5 v v dd 6 v 60 75 db supply current i dd 3.5 5.5 ma power dissipation p dis 55 mw notes 1 outputs are capable of sinking and sourcing over 20 ma, but linearity and offset are guaranteed at specified load levels. 2 all input control signals are specified with t r = t f = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 3 this parameter is guaranteed without test. 4 slew rate is measured in the sample mode with a 0 v to 10 v step from 20% to 80%. 5 slew rate is measured in the sample mode with a C3 v to +3 v step from 20% to 80%. specifications are subject to change without notice. rev. d C2C (@ v dd = +12.0 v, v ss = dgnd = 0 v, r l = no load, t a = operating temperature range specified in absolute maximum ratings, unless otherwise noted.) (@ v dd = +5.0 v, v ss = C5.0 v, dgnd = 0.0 v, r l = no load, t a = operating temperature range specified in absolute maximum ratings, unless otherwise noted.) smp04 C3C rev. d absolute maximum ratings (t a = +25 c unless otherwise noted) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, 17 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.7 v, 17 v v logic to dgnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd v in to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd v out to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd analog output current . . . . . . . . . . . . . . . . . . . . . . . 20 ma (not short-circuit protected) digital input voltage to dgnd . . . . . . . C0.3 v, v dd + 0.3 v operating temperature range eq, ep, es . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . +300 c package type u ja * u jc units 16-lead cerdip 94 12 c/w 16-lead plastic dip 76 33 c/w 16-lead so 92 27 c/w * u ja is specified for worst case mounting conditions, i.e., u ja is specified for device in socket for cerdip and plastic dip packages; u ja is specified for device soldered to printed circuit board for so package. caution 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; function operation at or above this specification is not implied. exposure to the above maximum rating conditions for extended periods may affect device reliability. 2. digital inputs and outputs are protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. keep units in conductive foam or packaging at all times until ready to use. use proper antistatic handling procedures. 3. remove power before inserting or removing units from their sockets. ordering guide temperature package package model range description options* smp04eq C40 c to +85 c cerdip-16 q-16 smp04ep C40 c to +85 c pdip-16 n-16 smp04es C40 c to +85 c so-16 r-16a *q = cerdip; n = plastic dip; r = small outline. pin connections 16-lead cerdip 16-lead plastic dip 16-lead so 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) smp04 nc = no connect v out2 v ss v out4 v out3 v dd v out1 v in1 nc s/h 4 v in3 v in4 v in2 s/h 1 s/h 2 dgnd s/h 3 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the smp04 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device C4C smp04 rev. d wafer test limits smp04g parameter symbol conditions limits units buffer offset voltage v os v in = +6 v 10 mv max hold step v hs v in = +6 v 4 mv max droop rate d v/ d tv in = +6 v 25 mv/s max output source current i source v in = +6 v 1.2 ma min output sink current i sink v in = +6 v 0.5 ma min output voltage range ovr r l = 20 k w 0.06/10.0 v min/max r l = 10 k w 0.06/9.5 v min/max logic characteristics logic input high voltage v inh 2.4 v min logic input low voltage v inl 0.8 v max logic input current i in 1 m a max supply characteristics power supply rejection ratio psrr 10.8 v v dd 13.2 v 60 db min supply current i dd 7 ma max power dissipation p dis 84 mw max note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. (@ v dd = +12 v, v ss = dgnd = 0 v, r l = no load, t a = +25 8 c, unless otherwise noted.) v out3 v out1 v out2 v out4 v in1 v in2 v in3 v in4 s/h 1 s/h 3 s/h 4 dgnd v ss v dd s/h 2 dice characteristics die size: 0.80 x 0.120 mil = 9,600 sq. mil (2.032 x 3.048mm = 6.193 sq. mm) typical performance characteristicsCsmp04 C5C rev. d input voltage C volts droop rate C mv/s 5 3 C5 01 10 23456789 1 C1 C3 0 v dd = +12v v ss = 0v figure 2. droop rate vs. input voltage (t a = +25 c) temperature C 8 c hold step C mv 3 C3 C55 C35 125 C15 5 25 65 85 105 45 2 1 0 C1 C2 v dd = +12v v ss = 0v v in = +5v figure 5. hold step vs. temperature input voltage C volts offset voltage C mv 20 5 C20 01 10 23456789 15 10 C5 C15 0 C10 v dd = +12v v ss = 0v r l = r l = 10kv r l = 20kv figure 8. offset voltage vs. input voltage (t a = +125 c) input voltage C volts droop rate C mv/s 1800 1200 600 01 10 23456789 1600 1400 1000 800 v dd = +12v v ss = 0v figure 3. droop rate vs. input voltage (t a = +125 c) slew rate C v/ms 7 6 3 10 11 18 12 13 14 15 16 17 5 4 v dd C volts t a = +25 8c v ss = 0v Csr +sr figure 6. slew rate vs. v dd input voltage C volts offset voltage C mv 4 C10 01 10 23456789 2 0 C2 C4 C6 C8 v dd = +12v v ss = 0v r l = r l = 20kv r l = 10kv figure 9. offset voltage vs. input voltage (t a = C55 c) temperature C 8 c droop rate C mv/s 10000 1000 0 C55 C35 125 C15 5 25 65 85 105 45 100 10 v dd = +12v v ss = 0v v in = +5v r l = 10kv figure 1. droop rate vs. temperature input voltage C volts hold step C mv 3 0 C3 01 10 23456789 2 1 C1 C2 t a = +258 c v dd = +12v v ss = 0v figure 4. hold step vs. input voltage input voltage C volts offset voltage C mv 2 C1 C4 01 10 23456789 1 0 C2 C3 v dd = +12v v ss = 0v r l = r l = 10kv r l = 20kv figure 7. offset voltage vs. input voltage (t a = +25 c) C6C smp04 rev. d temperature C 8 c offset voltage C mv 0 C1 C5 C55 C33 125 C15 5 25 65 85 105 45 C2 C3 C4 v dd = +12v v ss = 0v v in = +5v r l = 10kv figure 10. offset voltage vs. temperature frequency C hz gain C db 2 1 C5 100 1k 10m 10k 100k 1m C1 C2 C3 C4 0 phase gain 90 45 0 C45 C90 C135 C180 C225 phase shift C degrees figure 13. gain, phase shift vs. frequency v dd C volts supply current C ma 7 1 46 18 8 10121416 6 5 4 3 2 C558 c +258 c +1258 c r l = v ss = 0v figure 11. supply current vs. v dd frequency C hz output impedance C v 35 30 0 10 100 1m 1k 10k 100k 20 15 10 5 25 figure 14. output impedance vs. frequency frequency C hz rejection ratio C db 90 80 0 10 100 1m 1k 10k 100k 40 30 20 10 70 50 60 +pssr Cpssr v dd = +12v v ss = 0v v in = +6v figure 12. sample mode power supply rejection frequency C hz peak-to-peak output C volts 15 12 0 10k 100k 10m t a = +258c v dd = +6v v ss = C6v 1m 9 6 3 figure 15. maximum output voltage vs. frequency smp04 C7C rev. d general information the smp04 is a quad sample-and-hold with each track-and- hold having its own input, output, control, and on-chip hold capacitor. the combination of four high performance track-and- hold capacitors on a single chip greatly reduces board space and design time while increasing reliability. after the device selection, the primary considerations in using track-and-holds are the hold capacitor and layout. the smp04 eliminates most of these problems by having the hold capacitors internal, eliminating the problems of leakage, feedthrough, guard ring layout and dielectric absorption. power supplies the smp04 is capable of operating with either single or dual supplies over a voltage range of 7 to 15 volts. based on the supply voltages chosen, v dd and v ss establish the output volt- age range, which is: v ss + 0.05 v v out v dd C2 v note that several specifications, including acquisition time, offset and output voltage compliance will degrade for a total supply voltage of less than 7 v. positive supply current is typi- cally 4 ma with the outputs unloaded. the smp04 has an inter- nally regulated ttl supply so that ttl/cmos compatibility will be maintained over the full supply range. single supply operation grounding considerations in single supply applications, it is extremely important that the v ss (negative supply) pin be connected to a clean ground. this is because the hold capacitor is internally tied to v ss . any noise or disturbance in the ground will directly couple to the output of the sample-and-hold, d egrading the signal-to-noise performance. it is advisable that the analog and digital ground traces on the circuit board be physically separated to reduce digital switching noise from entering the analog circuitry. power supply bypassing for optimum performance, the v dd supply pin must also be bypassed with a good quality, high frequency ceramic capacitor. the recommended value is 0.1 m f. in the case where dual sup- plies are used, v ss (negative supply) bypassing is particularly important. again this is because the internal hold capacitor is tied to v ss . good bypassing prevents high frequency noise from entering the sample-and-hold amplifier. a 0.1 m f ceramic bypass capacitor is generally sufficient. for high noise environments, adding a 10 m f tantalum capacitor in parallel with the 0.1 m f provides additional protection. power supply sequencing it may be advisable to have the v dd turn on prior to having logic levels on the inputs. the smp04 has been designed to be resis- tant to latch-up, but standard precautions should still be taken. output buffers (pins 1, 2, 14 and 15) the buffer offset specification is 10 mv; this is less than 1/2 lsb of an 8-bit dac with 10 v full scale. change in offset over the output range is typically 3 mv. the hold step is the magnitude of the voltage step caused when switching from sample-to-hold mode. this e rror is sometimes referred to as the pedestal error or sample-to-hold offset, and is about 2 mv with little variation. the droop rate of a held channel is 2 m v/ms typical and 25 m v/ ms maximum. the buffers are designed primarily to drive loads connected to ground. the outputs can source more than 1.2 ma each, over the full voltage range and maintain specified accuracy. in split supply operation, symmetrical output swings can be obtained by restricting the output range to 2 v from either supply. on-chip smp04 buffers eliminate potential stability problems associated with external buffers; outputs are stable with capaci- tive loads up to 500 pf. however, since the smp04s buffer outputs are not short-circuit protected, care should be taken to avoid shorting any output to the supplies or ground. signal input (pins 3, 5, 11 and 12) the signal inputs should be driven from a low impedance voltage source such as the output of an op amp. the op amp should have a high slew rate and fast settling time if the smp04s fast acquisition time characteristics are to be maintained. as with all cmos devices, all input voltages should be kept within range of the supply rails (v ss v in v dd ) to avoid the possibil- ity of setting up a latch-up condition. the internal hold capacitance is typically 60 pf and the internal switch on resistance is 2 k w . if single supply operation is desired, op amps such as the op183 or ad820, that have input and output voltage compliances including ground, can be used to drive the inputs. split sup- plies, such as 7.5 v, can be used with the smp04 and the above mentioned op amps. application tips all unused digital inputs should be connected to logic low and the analog inputs connected to analog ground. for connec- tors or driven analog inputs that may become temporarily dis- connected, a resistor to v ss or analog ground should be used with a value ranging from 0.2 m w to 1 m w . do not apply signals to the smp04 with power off unless the input currents value is limited to less than 10 ma. track-and-holds are sensitive to layout and physical connections. for the best performance, the smp04 should not be socketed. C8C smp04 rev. d optimizing dynamic performance of the smp04 various operating parameters such as input voltage amplitude, sampling pulsewidth and, as mentioned before, supply bypass- ing and grounding all have an effect on the signal-to-noise ratio. table i shows the snr versus input level for the smp04. distortion of the smp04 is reduced by increasing the supply voltage. this has the effect of increasing the positive slew rate. table ii shows data taken at 12.3 khz sample rate and 2 khz input frequency. total harmonic distortion is dominated by the second and third harmonics. frequency domain performance the smp04 has been characterized in the frequency domain for those applications that require capture of dynamic signals. see figure 16a for typical 86.1 khz sample rate and an 8 khz input signal. typically, the smp04 can sample at rates up to 85 khz. in addition to the maximum sample rate, a minimum sample pulsewidth will also be acceptable for a given design. our testing shows a drop in performance as the sample pulsewidth becomes less than 4 m s. 10 db/div range 15.0 dbm 6.0 dbm start 1 000.0 hz stop 100 000.0 hz a. 10 db/div range 15.0 dbm 6.3 dbm start 1 000.0 hz stop 100 000.0 hz b. figure 16. spectral response at a sampling frequency of 86 khz. photo (a) shows a 20 khz carrier frequency and photo (b) shows an 8 khz frequency. table iii shows the effect of sampling pulsewidth on the snr of the smp04. the recommended operating pulsewidth should be a minimum of 5 m s to achieve a good balance between acqui- sition time and snr for the 1.4 v p-p signal shown. for larger swings the pulsewidth will need to be larger to account for the time required for the signal to slew the additional voltage. this could be used as a method of measuring acquisition time indirectly. table i. snr vs. v in input voltage snr (v p-p) (db) 1 C61 2 C53 3 C50 4 C47 5 C45 6 C44 conditions: v s = 6 v, f s = 14.4 khz, f in = 1.8 khz, t pw = 10 m s. table ii. snr vs. supply voltage supply voltage 2nd 3rd (v) (db) (db) 10 C49 C62 12 C55 C71 14 C60 C80 15 C62 C10C smp04 rev. d applications multiplexed quad dac (figure 20) the smp04 can be used to demultiplex a single dac converters output into four separate analog outputs. the circuit is greatly simplified by using a voltage output dac such as the dac8228. to minimize output voltage perturbation, 5 m s should be allowed to settle to its final voltage before a sample signal is asserted. each sample-and-hold amplifier must be refreshed every second or less in order to assure the droop does not exceed 10 mv or 1/2 lsb. channel decode v ss v out1 v out2 v out3 v out4 dgnd v ss v ss v ss smp04 1mf +12v ref02 +12v 0.1mf 1/2 dac8228 v z +5v gnd v dd v ref v o digital inputs address inputs s/h 1 s/h 2 s/h 3 s/h 4 +12v 5v to 10v wr cs + figure 20. multiplexed quad dac smp04 C11C rev. d positive and negative peak detector with hold control (figure 21) in this application the top amplifier (amplifier a) is the positive peak detector and the bottom amplifier (amplifier b) is the negative peak detector. operation can be analyzed as follows: assume that the s /h switch is closed. as a positive increasing voltage is applied to v in , d 2 turns on, and d 1 turns off, closing the feedback loop around amplifier a and the smp04, causing the output to track the input. conversely, in the negative peak detector circuit at the bottom, d 4 turns off and d 3 turns on, holding the last most negative input voltage on the smp04. this voltage is buffered to the v o(neg) output. as v in falls in voltage the above conditions reverse, causing the most positive peak voltage to be held at v o(pos) output. this voltage will be held until the input has a more positive voltage than the previously held peak voltage, or a reset condition is applied. an optional hold control can be used by applying a logic high to the pd/h inputs. this hold mode further reduces leakage current through the reverse-biased diodes (d 2 and d 4 ) during peak hold. v out negative v ss dgnd v ss v ss C5v +5v 1/2 op221 1/2 op221 C5v +5v v out positive amplifier a amplifier b r1 20kv d 1 1n914 d 2 v dd 1/2 smp04 r2 100v d s q 1 sd214 v in (6 3.5v) reset pd/h positive pd/h negative sd214 r3 20kv d 3 1n914 r4 100v d s q 2 d 4 g g figure 21. positive and negative peak detector with hold control gain of 10 sample-and-hold (figure 22) this application places the smp04 in a feedback loop of an amplifier. because the smp04 has no sign inversion and the amplifier has very high open-loop gain, the gain of the circuit is set by the ratio of the sum of the source and feedback resistances +12v v ss 1/4 op490 +12v v out 0v to 10v 1/4 smp04 1kv v in 0v to 1.0v s/h 100kv 1n914 8.66kv 340v figure 22. gain of 10 sample-and-hold amplifier to the source resistance. when a logic low is applied to the s /h cont rol input, the loop is closed around the op490, yielding a gain of 10 (in the example shown) amplifier. when the s /h control goes high, the loop opens and the smp04 holds the last sampled voltage. the loop remains open and the output is unaffected by the input until a logic low is reapplied to the s /h control. the pair of back-to-back diodes from the output of the op amp to the output of the track-and-hold pre- vents the op amp from saturating when the track-and-hold is in the hold mode and the loop is open. C12C smp04 rev. d sample and difference amplifier (figure 23) this circuit uses two sample-and-holds to measure the voltage difference of a signal between two time points, t 1 and t 2 . the sampled voltages are fed into the differential inputs of the amp02 instrumentation amplifier. a single resistor r g sets the gain of this in strumentation amplifier. using two channels of the smp04 in this application has the advantage of matched sample-a nd-hold performance, since they are both on the same chip. v ss dgnd v ss v ss +12v v dd 1/2 smp04 amp02 v 1 v 2 r g +12v C5v or C12v v out = g(v1Cv2) g = +1 50kv r g v in (0v to 8v) s/h (delayed) s/h v 1 v 2 t 1 t 2 t d 0 0 instrumentation amp figure 23. time delta sample-and-difference measurement single supply, sampling, instrumentation amplifier (figure 24) this application again uses two channels of the smp04 and an instrumentation amplifier to provide a sampled difference signal. the sample-and-hold signals in this circuit are tied together to sample at the same point in time. the other two parts of the smp04 are used as amplifiers by grounding their control lines so they are always sampling. one section is used to drive a guard to the common-mode voltage and the other to generate a +6 v reference to serve as an offset for single supply operation. +6v reference reference v out amp02 1/4 smp04 1/4 smp04 1/4 smp04 1/4 smp04 0.1mf gain = 50kv r g +1 r g 50kv 50kv +12v 20kv 20kv 0.01mf guard guard guard drive s/h + input C input +12v +12v figure 24. +12 v single supply sampling instrumentation amplifier with guard drive smp04 C13C rev. d d/a converter deglitcher most d/a converters output an appreciable amount of glitch energy during a transition from one code to another. the glitch amplitude can range from several millivolts to hundreds of milli- volts. this may become unacceptable in many applications. by selectively delaying the dacs output transition, the smp04 can be used to smooth the output waveform. figure 25 shows the schematic diagram of such a deglitcher circuit. two simple logic gates (an or and a nand gate) provide the proper timing sequence for the dac wr strobe and the s /h control signal to the smp04. in this example a linear ramp signal is generated by feeding the most significant eight bits of the 10-bit binary counter to the dac. the two least significant bits are used to produce the delayed wr strobe and the s /h control signals. referring to figure 26a, new data to the dac input is set up at the s /hs falling edge, but the dac output does not change until a wr strobe goes active. during this period, the smp04 is in a sample mode whose output tracks the dac output. when s /h goes high, the current dac output voltage is held by the smp04. after 1.2 m s settling, the wr strobe goes low to allow the dac output to change. any glitch that occurs at the dac output is effectively blocked by the smp04. as soon as the wr strobe goes high, the digital data is latched; at the same time the s /h goes low, allowing the smp04 to track to the new dac output voltage. figure 26b shows the deglitching operation. the top trace shows the dac output during a transition, while the bottom trace shows the deglitched output of the smp04. 1/4 smp04 10-bit counter clock generator db 2 Cdb 9 db 0 deglitch logic 1/4 ad7432 1/4 ad7400 a 1 a 0 v dd v ref out dac c out 1/4 dac8426 v ss agnd dgnd wr +5v +15v 1mf agnd 0.1mf 0.1m fC1m f ceramic v out +15v dgnd s/h db 9 db 2 v dd v ss lsb msb v in digital return analog return db 1 figure 25. dac deglitcher 1 m s 5v db 0 db 1 wr s/h a. 1 m s 50m dly 627.4 m s b. figure 26. (a) shows the logic timing of the deglitcher. the top two traces are the two least significant bits, db 0 and db 1 , respectively. these are used to generate the wr and s /h signals which are shown in the bottom two traces. (b) shows the typical glitch amplitude of a dac (top trace) and the deglitched output of the amp04 (bottom trace). C14C smp04 rev. d load v out n-ch p-ch v in v dd s/h v ss dgnd logic v dd v ss c h figure 27. simplified schematic of one channel r2 10kv smp04 1 2 3 5 6 7 89 10 11 12 13 14 15 16 r4 1kv r2 10kv d 1 v dd +15v r2 10kv r2 10kv + r3 4kv r1 10v c1 10mf c2 1mf figure 28. burn-in circuit smp04 C15C rev. d outline dimensions dimensions shown in inches and (mm). 16-lead cerdip (q-16) 16 1 8 9 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.080 (2.03) max seating plane 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 16-lead plastic dip (n-16) 16 18 9 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead so (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 printed in u.s.a. c3131C0C4/98 |
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